Job description:High Volum RFIC frontend component design for cellular and infrastructure applications.
Meet Specification, schedual and target cost.Balance between performance, yield, and cost.Knowledge of Keysight/Agilent ADS, Cadence Virtuoso for circuit design.
Prepare Quality engineering documents for peers, customers and managementInteract with different peers within our company, a team player.
QUALIFICATIONS:Minimum BSEE in RFIC/Electronics or telecommunication field.Circuit design knowledge in two or more of the following: SOI Switch, SOI/CMOS LNA, GaAs/SOI Power Amplifier, Filters, Analog/Mixed Signal design.MonteCarlo and PVT simulation.
Problem-solving skills and ownership
Strong communication and presentation skills.
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